1. Field of the Invention
The present invention relates to semiconductor technology, and particularly, relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Description of Related Art
In the process of manufacturing Complementary Metal-Oxide Semiconductor (CMOS), with the scaling of the critical dimension of semiconductor devices, stress is typically introduced into the channel region for improving mobility of carriers and performance of semiconductor devices.
The following table is shown by Scott E. Thompson et al. in Uniaxial-Process-Induced Strained-Si: Extending the CMOS Roadma (IEEE Transactions on Electron Devices, Vol 53, No. 5, February 2006).
Unit: 10−12 cm2/dyn(001) silicon<100><110>polarityπ∥π⊥π∥π⊥π11π12(π11 + π12 +(π11 + π12 −π44)/2π44)/2n-MOSFET−42.6/−102−20.7/53.4−35.5/−31.6−14.5/−17.6p-MOSFET 9.1/6.6 −6.2/−1.171.7/71.8−33.8/−66.3
The table shows comparison of piezoresistance coefficients between a MOSFET on a silicon chip of crystal indices (001) and bulk silicon. The piezoresistance coefficients are well known in the semiconductor technology for predicting and measuring mobility of electrons and holes. In the table, π∥ is the piezoresistance coefficient in the longitudinal direction, and π⊥ is the piezoresistance coefficient in the transverse direction of the channel region. As for a silicon chip having a crystal indices (001), π∥ and π⊥ may be expressed as functions of three fundamental cubic piezoresistance coefficients π11, π12 and π44, respectively. The influence of piezoresistance coefficients on mobility of carriers may be expressed as: Δμ/μ≈|π∥σ∥+π⊥σ⊥, wherein Δμ/μ is the fractional change in mobility, σ∥ and σ⊥ are longitudinal and transverse stresses of the channel region, respectively. As shown in the above table, the tensile stress in transverse direction of the channel region enhances mobility of carriers for both PMOS transistors and NMOS transistors.
However, in related art, stress is typically introduced in the longitudinal direction of the channel region, for example, by Dual Stress Liner (DSL) technology and Stress Memorization Technology (SMT), and so on.
Taking the DSL technology as an example, an NMOS transistor is covered by a tensile stress liner, and a PMOS transistor is covered by a compressive stress liner, thereby improving mobility of carriers in the NMOS transistor and PMOS transistor, respectively. Therefore, in the manufacturing process, the DSL technology requires formation of respective stress liners for different types of transistors, which is complicated. The SMT requires forming stress liners on devices firstly and then performing an annealing process to the devices, which is also complicated.
Therefore, a new type of semiconductor device is needed to solve the above problems existing in the related art, in order that stress is more sufficiently applied to MOS transistors, and performance of the MOS transistors may be improved.